1. Field of the Invention
The present invention relates to cache architectures, and more particularly to write combining caches.
2. Background Art
As the use of computer systems has increased, so has the desire for increased performance. Faster processors and computer systems are being developed to meet the needs of users throughout the world. One feature commonly found in processors to increase their performance is one or more cache memories. A cache memory is a memory unit that is smaller than the system memory (or the next higher level cache memory), but that operates at a faster speed than the system memory (or the next higher level cache memory). The goal of the cache memory is to contain the information (whether it be data or operations) that the execution unit(s) of the processor is going to use next. This information can then be returned to the execution unit(s) much more quickly, due to the higher speed of the cache memory.
When necessary, modified data from the cache is written back to the higher level system memory. In some cases, it may be necessary to have multiple memories in order to optimize transfer of data from cache to memory. As each of the writes is passed, for example, through a first cache memory to a second cache memory, a large amount of data is transferred between the two memories. One solution to this data traffic problem is to use a write combining cache to temporarily store write data from the first cache memory to the second cache memory or to system memory directly.
Conventionally, cache memories or write combining buffers operate in a manner that does not allow for concurrent update of data in the cache or write combining buffer, while data is being transmitted or “flushed” to the higher level memory. These conventional approaches may stall incoming data and prevent any new cache-lines from entering a cache while cache-lines are being flushed out to memory.
Therefore, conventional approaches synchronize cache memories or write combining buffers in a manner where a cache, or a write combining buffer, cannot be updated with data unless data previously present therein is flushed to a memory. This form of conventional synchronization may degrade any performance optimization that can be achieved by the use of one or more cache memories or write combining buffers.
What is needed, therefore, are improved methods and systems for synchronizing data in a write combining cache.